2.7. Intel® Agilex™ Configuration Time Estimation
The table provides time estimates for the full FPGA configuration only. In HPS enabled designs, the table also considers the FPGA configuration first mode. Note that the HPS boot first mode in HPS enabled designs is not considered. Also, the CvP periphery image configuration is not considered. In general, if you use the Micron flash device for AS x4 configuration, the CvP periphery image configuration time is expected to be less than 100 ms.
- Set the VID mode of operation to PMBus Master mode
- Use Intersil ISL68137 regulator to regulate the PMBus
- Set configuration clock source to OSC_CLK_1 with 25/100/125 MHz
- No advanced security features were enabled
- For AVST x8/x16/x32 configuration modes, set the AVST_CLK to 125 MHz. The external host controller supplies the AVST_DATA by asserting the AVST_VALID signal high whenever the AVST_READY signal is high.
- For AS x4 configuration mode, set the AS_CLK to 166 MHz. Use a Micron device with a 2 Gb density range QSPI flash memory.
|Device||Bitstream File Size (MB)||Configuration Time Estimation (ms)|
|AS x4 7||AVST x8||AVST x16|
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