Intel® Agilex™ Configuration User Guide

ID 683673
Date 7/05/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1.7.3.4. Creating Separate PFL II Functions

Follow these steps to create separate PFL II IP instantiations for programming and configuration control:
  1. In the IP Catalog locate the Parallel Flash Loader II Intel FPGA IP.
  2. On the General tab for What operating mode will be used, select Flash Programming Only.
  3. Intel recommends that you turn on the Set flash bus pins to tri-state when not in use.
  4. Specify the parameters on the Flash Interface Settings and Flash Programming tabs to match your design.
  5. Compile and generate a .pof for the flash memory device. Ensure that you tri-state all unused I/O pins.
  6. To create a second PFL II instantiation for FPGA configuration, on the General tab, for What operating mode will be used, select FPGA Configuration.
  7. Use this Flash Programming Only instance of the PFL II IP to write data to the flash device.
  8. Whenever you must program the flash memory device, program the CPLD with the flash memory device .pof and update the flash memory device contents.
  9. Reprogram the CPLD with the production design .pof that includes the configuration controller.
    Note: By default, all unused pins are set to ground. When programming the configuration flash memory device through the host JTAG pins, you must tri-state the FPGA configuration pins common to the host and the configuration flash memory device. You can use the pfl_flash_access_request and pfl_flash_access_granted signals of the PFL II block to tri-state the correct FPGA configuration pins.

Did you find the information on this page useful?

Characters remaining:

Feedback Message