Intel® Agilex™ Configuration User Guide

ID 683673
Date 7/05/2022
Public

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2.5. Intel® Agilex™ Configuration Pins

The Intel® Agilex™ device uses SDM_IO pins for device configuration. Control of SDM I/O pins passes from internal FPGA circuitry, to the Boot ROM, and finally to the value your application logic specifies.
  1. After power-on, SDM I/O pins 0, 8, and 16 have weak pull-downs. All other SDM I/O pins have weak pull-ups. (These initial voltage levels ensure correct operation during initialization. For example, for Avalon® -ST configuration SDM_IO8 is the Avalon® -ST ready signal which should not be asserted until the device reaches the FPGA Configuration state.)
  2. The Boot ROM samples MSEL to determine the configuration scheme you specified and drives pins required for that configuration scheme. SDM I/O pins not required for your configuration scheme remain weakly pulled up.
  3. In approximately 10 ms the SDM I/O pins take on the state that your design specifies.
  4. After device cleaning, the SDM reads pin information from firmware and restores the pin states that your design specifies. If you reconfigure the device, the SDM uses the updated pin information when initializing the device.

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