Intel® Agilex™ Configuration User Guide

ID 683673
Date 7/05/2022
Public

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2.5.3.2. Enabling Dual-Purpose Pins

AVST_CLK, AVST_DATA[15:0], AVST_DATA[31:16], and AVST_VALID are dual-purpose pins. Once the device enters user mode these pins can function either as GPIOs or as tri-state inputs.
If you use these pins as GPIOs, make the following assignments:
  • Set VCCIO of the I/O bank at 1.2 V
  • Assign the 1.2 V I/O standard to these pins

Complete the following steps to assign these settings to the dual-purpose pins:

  1. On the Assignments menu, click Device.
  2. In the Device and Pin Options dialog box, select the Dual-Purpose Pins category.
  3. In the Dual-purpose pins table, set the pin functionality in the Value column.
  4. Click OK to confirm and close the Device and Pin Options
    Attention: When you use the Avalon® ST configuration scheme the dual-purpose Avalon® ST pins have the following restrictions:
    • You cannot use the Avalon® -ST interface for partial reconfiguration (PR).
    • You cannot use the Avalon® -ST pins in user mode in designs that include the HPS. This restriction means that you cannot use the Avalon® -ST as dual-purpose I/Os in designs that include the HPS.
    Table 7.  Dual-Purpose Pin Restrictions for Avalon Streaming x16 and x32 Configuration Schemes
    Dual-Purpose Pin Avalon Streaming x16 Avalon Streaming x32
    Not Used in User Mode Used in User Mode Not Used in User Mode Used in User Mode
    AVST_CLK Setting: As input tri-stated Setting: Set as regular I/O

    Pin Connection: Set as Input and assign ALL pins in pin assignment

    Setting: As input tri-stated

    Setting: Set as regular I/O

    Pin Connection: Set as Input and assign ALL pins in pin assignment

    AVST_VALID
    AVST_DATA[15:0]
    AVST_DATA[31:16] No restrictions
    Note:
    • All pins in the same group name must be assigned to the physical pin in pin assignment. For instance, if only 2 out of 16 pins from AVST_DATA[15:0] are used, then all 16 pins must be assigned to physical pins including the unused pins in the user design.
    • All pins with pin assignments must be in known state, whether weak pull-up or weak pull-down.
    • The dual-purpose pin restrictions are not applicable to Intel® Agilex™ AGF 006/008/012/014/022/027 and AGI 022/027 devices.

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