6.2. Configuration via Protocol
The CvP configuration scheme creates separate images for the periphery and core logic. You can store the periphery image in a local configuration device and the core image in host memory, reducing system costs and increasing the security for the proprietary core image. CvP configures the FPGA fabric through the PCI Express* ( PCIe* ) link and is available for Endpoint variants only.
The CvP configuration scheme supports the following modes:
- CvP Initialization Mode:
In this mode an external configuration device stores the periphery image and it loads into the FPGA through the Active Serial x4 (Fast mode) configuration scheme. The host memory stores the core image and it loads into the FPGA through the PCIe* link.
After the periphery image configuration completes, the CONF_DONE signal goes high and the FPGA starts PCIe* link training. When PCIe* link training completes, the PCIe* link transitions to the Link Training and Status State Machine (LTSSM) L0 state and then through PCIe* enumeration. The PCIe* host then configures the core through the PCIe* link. The PCIe* reference clock must be running for the link for link training.
After the core image configuration is complete, the CvP_CONFDONE pin (if enabled) goes high, indicating the FPGA has received the full configuration bitstream over the PCIe* link. INIT_DONE indicates that configuration is complete.
- CvP Update Mode:
CvP update mode is a reconfiguration scheme that uses the PCIe* link to deliver an updated bitstream to a target device after the device enters user mode. The periphery images which includes the PCIe* link remains active, allowing CvP update to use this link to reconfigure the core fabric. In this mode, the FPGA device initializes by loading the full configuration image from the external local configuration device to the FPGA or after CvP initialization.
You can perform CvP update on a device that you originally configure using CvP initialization or any other configuration scheme.
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