Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

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7.11.1.2. Avalon® Memory Mapped Control and Status Register Interface

You can configure the single-clock FIFO IP to include an optional Avalon® memory mapped interface, and the dual-clock FIFO IP to include an Avalon® memory mapped interface in each clock domain. The Avalon® memory mapped interface provides access to 32-bit registers, which allows you to retrieve the FIFO buffer fill level and configure the almost-empty and almost-full thresholds. In the single-clock FIFO IP, you can also configure the packet and error handling modes.