Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

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7.4.2. Avalon® Data Pattern Checker Intel® FPGA IP

The Avalon® Data Pattern Checker Intel® FPGA IP accepts data via an Avalon® streaming interface and verifies it against a predetermined pattern that the Avalon® Data Pattern Generator Intel® FPGA IP produces. The Avalon® Data Pattern Checker IP reports any exceptions to the control interface. You can parameterize most aspects of the Avalon® Data Pattern Checker's Avalon® streaming interface, such as the number of error bits, and the data signal width. This IP allows you to test components with different interfaces. The Avalon® Data Pattern Checker IP has a throttle register that is set via the Avalon® memory mapped control interface. The value of the throttle register controls the rate at which data is accepted.

Figure 229.  Avalon® Data Pattern Checker Intel® FPGA IP

The Avalon® Data Pattern Checker IP detects exceptions and reports them to the control interface via a 32-element deep internal FIFO. Possible exceptions are data error, missing start-of-packet (SOP), missing end-of-packet (EOP), and signaled error.

As each exception occurs, an exception descriptor is pushed into the FIFO. If the same exception occurs more than once consecutively, only one exception descriptor is pushed into the FIFO. All exceptions are ignored when the FIFO is full. Exception descriptors are deleted from the FIFO after they are read by the control and status interface.