Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

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7.2.2.3. CSR Read Access Violation Log Registers

The CSR read access violation log settings are valid only when an associated read interrupt register is set. Read this set of registers until the validity bit is cleared.
Table 131.  CSR Read Access Violation Log Registers
Offset Bits Attribute Default Description
0x100 31:13 Reserved.
12:11 R0 0 Offending Read cycle burst type: Specifies the burst type of the initiating cycle that causes the access violation.
10:7 R0 0 Offending Read cycle burst length: Specifies the burst length of the initiating cycle that causes the access violation.
6:4 R0 0 Offending Read cycle burst size: Specifies the burst size of the initiating cycle that causes the access violation.
3:1 R0 0 Offending Read cycle PROT: Specifies the PROT of the initiating cycle that causes the access violation.
0 R0 0 Read cycle log valid: Specifies the validity of the read access violation log. This bit is cleared when the interrupt register is cleared.
0x104 31:0 R0 0 Offending read cycle ID: Manager ID for the cycle that causes the access violation.
0x108 31:0 R0 0 Offending read cycle target address: Target address for the cycle that causes the access violation (lower 32-bit).
0x10C 31:0 R0 0 Offending read cycle target address: Target address for the cycle that causes the access violation (upper 32-bit). Valid only if widest address in system is larger than 32 bits.
Note: When this register is read, the current read access violation log is recovered from FIFO.