Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

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5.7.4. Duration of Transfers Crossing Clock Domains

CDC logic extends the duration of host transfers across clock domain boundaries. In the worst case, which is for reads, each transfer is extended by five host clock cycles and five agent clock cycles. Assuming the default value of 2 for the host domain synchronizer length and the agent domain synchronizer length, the components of this delay are the following:

  • Four additional host clock cycles, due to the host-side clock synchronizer.
  • Four additional agent clock cycles, due to the agent-side clock synchronizer.
  • One additional clock in each direction, due to potential metastable events as the control signals cross clock domains.
Note: Systems that require a higher performance clock should use the Avalon® memory mapped clock crossing bridge instead of the automatically inserted CDC logic. The clock crossing bridge includes a buffering mechanism so that multiple reads and writes can be pipelined. After paying the initial penalty for the first read or write, there is no additional latency penalty for pending reads and writes, increasing throughput by up to four times, at the expense of added logic resources.