Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.5.4. Viewing Clock and Reset Domains

The Platform Designer Clock Domains and Reset Domains tabs list the clock and reset domains in the Platform Designer system, respectively.

Click View > Clock Domains or click View > Reset Domains to display these tabs.

Platform Designer determines clock and reset domains by the associated clocks and resets. This information displays when you hover over interfaces in your system.

The Clock Domains and Reset Domains tabs also allow you to locate system performance bottlenecks. The tabs indicate connection points where Platform Designer automatically inserts clock-crossing adapters and reset synchronizers during system generation. View the following information on these tabs to create optimal connections between interfaces:

  • The number of clock and reset domains in the system
  • The interfaces and modules that each clock or reset domain contains
  • The locations of clock or reset crossings
  • The connection point of automatically inserted clock or reset adapters
  • The proper location for manual insertion of a clock or reset adapter
Figure 12. Clock Domains, Reset Domains, and System View Tabs