Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

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7.2.2.4. CSR Write Access Violation Log Registers

The CSR write access violation log settings are valid only when an associated write interrupt register is set. Read this set of registers until the validity bit is cleared.
Table 132.  CSR Write Access Violation Log
Offset Bits Attribute Default Description
0x190 31:13 Reserved.
  12:11 R0 0 Offending write cycle burst type: Specifies the burst type of the initiating cycle that causes the access violation.
  10:7 R0 0 Offending write cycle burst length: Specifies the burst length of the initiating cycle that causes the access violation.
  6:4 R0 0 Offending write cycle burst size: Specifies the burst size of the initiating cycle that causes the access violation.
  3:1 R0 0 Offending write cycle PROT: Specifies the PROT of the initiating cycle that causes the access violation.
  0 R0 0 Write cycle log valid: Specifies whether the log for the transaction is valid. This bit is cleared when the interrupt register is cleared.
0x194 31:0 R0 0 Offending write cycle ID: Manager ID for the cycle that causes the access violation.
0x198 31:0 R0 0 Offending write cycle target address: Write target address for the cycle that causes the access violation (lower 32-bit).
0x19C 31:0 R0 0 Offending write cycle target address: Write target address for the cycle that causes the access violation (upper 32-bit). Valid only if widest address in system is larger than 32 bits.
0x1A0 31:0 R0 0 Offending write cycle first write data: First 32 bits of the write data for the write cycle that causes the access violation.
Note: When this register is read, the current write access violation log is recovered from FIFO, when the data width is 32 bits.
0x1A4 31:0 R0 0 Offending write cycle first write data: Bits [63:32] of the write data for the write cycle that causes the access violation. Valid only if the data width is greater than 32 bits.
0x1A8 31:0 R0 0 Offending write cycle first write data: Bits [95:64] of the write data for the write cycle that causes the access violation. Valid only if the data width is greater than 64 bits.
0x1AC 31:0 R0 0 Offending write cycle first write data: The first bits [127:96] of the write data for the write cycle that causes the access violation. Valid only if the data width is greater than 64 bits.
Note: When this register is read, the current write access violation log is recovered from FIFO.