Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

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8.2.1. qsys-generate Command-Line Options

Table 196.  Command-Line Options for qsys-generateOptions in alphabetical order.
Option Usage Description
<1st arg file> Required Specifies the name of the .qsys system file to generate.
--block-symbol-file Optional Creates a Block Symbol File (.bsf) for the Platform Designer system.
--clear-output-directory Optional Clears the output directory corresponding to the selected target, that is, simulation or synthesis.
--example-design=<value> Optional

Creates example design files.

For example, --example-design or --example-design=all. The default is All, which generates example designs for all instances. Alternatively, choose specific filesets based on instance name and fileset name. For example --example-design=instance0.example_design1,instance1.example_design 2. Specify an output directory for the example design files creation.
--family=<value> Optional Sets the device family name.
--help Optional Displays help for --qsys-generate.
--greybox Optional If you are synthesizing your design with a third-party EDA synthesis tool, generate a netlist for the synthesis tool to estimate timing and resource usage for this design.
Note: Generation of a timing and area estimation (gray box) netlist is available only for individual Intel FPGA IP, and not for Platform Designer systems.
--ipxact Optional If you specify this option, Platform Designer generates the post-generation system as an IPXACT-compatible component description.
Note: Platform Designer supports importing and exporting files in IP-XACT 2009 format and exporting IP-XACT files in 2014 format.
--jvm-max-heap-size=<value> Optional The maximum memory size that Platform Designer uses when running qsys-generate. You specify the value as < size><unit >, where unit is m (or M) for multiples of megabytes or g (or G) for multiples of gigabytes. The default value is 512m.
--parallel[=<level>] Optional Directs Platform Designer to generate in parallel mode, with the level of parallelism that you specify. If you omit the level, Platform Designer determines a number based on processor availability and number of files to be generated.
--part=<value> Optional Sets the device part number. If set, this option overrides the --family option.
--search-path=<value> Optional If you omit this command, Platform Designer uses a standard default path. If you provide this command, Platform Designer searches a comma-separated list of paths. To include the standard path in your replacement, use "$", for example, "/extra/dir,$".
--simulation=<VERILOG|VHDL> Optional Creates a simulation model for the Platform Designer system. The simulation model contains generated HDL files for the simulator, and may include simulation-only features. Specify the preferred simulation language. The default value is VERILOG.
--synthesis=<VERILOG|VHDL> Optional Creates synthesis HDL files that Platform Designer uses to compile the system in an Intel® Quartus® Prime project. Specify the generation language for the top-level RTL file for the Platform Designer system. The default value is VERILOG.
--testbench=<SIMPLE|STANDARD> Optional Creates a testbench system that instantiates the original system, adding bus functional models (BFMs) to drive the top-level interfaces. When you generate the system, the BFMs interact with the system in the simulator. The default value is STANDARD.
--testbench-simulation=<VERILOG|VHDL > Optional After you create the testbench system, create a simulation model for the testbench system. The default value is VERILOG.
--upgrade-ip-cores Optional Enables upgrading all the IP cores that support upgrade in the Platform Designer system you specify. This command has no impact on IP cores in any subsystem.
--upgrade-variation-file Optional If you set this option to true, the file argument for this command accepts a .v file, which contains a IP variant. This file parameterizes a corresponding instance in a Platform Designer system of the same name.