1. Introduction to Intel® FPGA Design Flow for AMD* Xilinx* Users
2. Technology Comparison
3. FPGA Tools Comparison
4. AMD* Xilinx* to Intel® FPGA Design Conversion
5. Conclusion
6. AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users Archives
7. Document Revision History for Intel® FPGA Design Flow for AMD* Xilinx* Users
3.3.1. Project Creation
3.3.2. Design Entry
3.3.3. IP Status
3.3.4. Design Constraints
3.3.5. Synthesis
3.3.6. Design Implementation
3.3.7. Finalize Pinout
3.3.8. Viewing and Editing Design Placement
3.3.9. Static Timing Analysis
3.3.10. Generation of Device Programming Files
3.3.11. Power Analysis
3.3.12. Simulation
3.3.13. Hardware Verification
3.3.14. View Netlist
3.3.15. Design Optimization
3.3.16. Techniques to Improve Productivity
3.3.17. Partial Reconfiguration
3.3.18. Cross-Probing in the Quartus® Prime Pro Edition Software
4.2.1.2.1. Memory Mode
4.2.1.2.2. Clocking Mode
4.2.1.2.3. Write and Read Operation Triggering
4.2.1.2.4. Read-During-Write Operation at the Same Address
4.2.1.2.5. Error Correction Code (ECC)
4.2.1.2.6. Byte Enable
4.2.1.2.7. Address Clock Enable
4.2.1.2.8. Parity Bit Support
4.2.1.2.9. Memory Initialization
4.2.1.2.10. Output Synchronous Set/Reset
4.2.2.2. Port Mapping Reference
The following table shows the mapping between MMCM UltraScale* ports, created with the AMD* Xilinx* IP Catalog, and PLL ports in Stratix® 10 device, created with the IP Catalog.
AMD* Xilinx* MMCM Core Port | Intel® FPGA Intel® FPGA IOPLL IP Core Port | Description |
---|---|---|
clk_in1 | refclk | First clock input |
clk_in2 | refclk1 | Second clock input |
clkfb_in | fbclk | External clock feedback |
clkfbout | fboutclk | Feeds into the feedback port |
— | activeclk | Output signal that indicates which reference clock source the I/O PLL uses |
clk_in_sel | extswitch | Switch between input clock ports |
reset | rst | Asynchronous reset port |
clk_out1, clk_out2, clk_outX | outclk_[] | Clock frequency output ports. AMD* Xilinx* MMCM has fixed settings for most outputs, and you can configure the Intel® FPGA IOPLL IP core to suit them. |
clkinstopped | clkbad[1..0] | Indicates whether the clock input signal stopped switching |
clkfb_stopped | — | Specifies whether the feedback clock stopped |
locked | locked | Specifies whether the PLL is locked |
— | adjpllin | Input signal that feeds from upstream I/O PLL |
— | cascade_out | Output signal that feeds into downstream I/O PLL |
— | zdbfbclk | Bidirectional port that connects to the mimic circuitry. You connect this port to a bidirectional pin that is placed on the positive feedback dedicated output pin of the I/O PLL. The zdbfbclk port is available only if the I/O PLL is in zero-delay buffer mode. |
AMD* Xilinx* MMCM Core Port | Dynamic Phase Shift Ports in Intel® FPGA IOPLL | Description |
---|---|---|
psclk | scanclk | Specifies clock that drives the dynamic phase shift operation |
psen | phase_en | Start dynamic phase-shift operation |
psincdec | updn | Specifies direction of phase shift operation |
— | cntsel | Specifies counter for dynamic phase shift operation |
— | num_phase_shift | Specifies number of phase shifts per dynamic phase shift operation |
psdone | phase_done | Specifies completion of dynamic phase shift operation |
power_down | — | Enables power_down input port for user selection |
For more information about using dynamic PLL reconfiguration, refer to the Phase-Locked Loops ( Intel® FPGA IOPLL) IP Core User Guide.