Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 2/06/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.7.1. Traffic Generator and checker Example Design Register Map

The Traffic generator and checker control and status registers are byte addresses. The Traffic generator checker register map is mapped to BAR0 in the Example Design..
Table 3.  Read start address (Offset 16’h0000)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31:0] RAdd R/W 0 This register contains the base addresses that the Traffic Checker reads from.
Table 4.  Read count (Offset 16’h0008)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] Mode R/W 0

0: Fixed no of transfers

1: non-stop transfers

[30:12] rsvd     Reserved
[11:0] RCnt R/W 0 Write to the RCnt registers to specify the number of transfers to execute. Reading from one of these registers returns the number of transfers that have occurred since it was last read.
Table 5.  Read error count (Offset 16’h0010)
Bit[63:0] Name R/W Default Description
[63:12] rsvd     Reserved
[11:0] RErr ROC 0 Reading the RErr register returns the number of errors detected since the register was last read. A maximum of one error is counted per clock cycle.
Table 6.  Read control (Offset 16’h0018)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] enable R/W 0 0: stop 1: start
[30:8] rsvd     Reserved
[7:0] transfer_size   0 This register configures the burst length per transfer (ideal value for x16 is 8 & x8 is 16). Zero is not a legal value.
Table 7.  Write start address (Offset 16’h0020)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31:0] WAdd R/W 0 This register contains the base addresses that the Traffic Generator writes to.
Table 8.  Write count (Offset 16’h0028)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] Mode R/W 0

0: Fixed no of transfers

1: non-stop transfers

[30:12] rsvd     Reserved
[11:0] WCnt R/W 0 Write to the WCnt registers to specify the number of transfers to execute. Reading from one of these registers returns the number of transfers that have occurred since it was last read.
Table 9.  Write error count (Offset 16’h0030)
Bit[63:0] Name R/W Default Description
[63:12] rsvd     Reserved
[11:0] WErr ROC 0 Reserved (Write error detection not available yet). Because the write error detection feature is not available yet, you cannot get a valid number of errors by reading the WErr register.
Table 10.  Write control (Offset 16’h0038)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] enable R/W 0 0: stop 1: start
[30:8] rsvd     Reserved
[7:0] transfer_size   0 This register configures the burst length per transfer (ideal value for x16 is 8 & x8 is 16). Zero is not a legal value.
Table 11.  Read address mapping table (Offset 16’h0100)The Read address mapping table is 32 locations and 64bit wide each.
Bit[63:0] Name R/W Default Description
[63:0] raDM R/W 0 This register contains the Traffic Checker address mapping table that maps thirty-two 1 MB regions of the Avalon-MM memory space into thirty-two 1 MB regions of the PCIe address space. The module occupies only 32MB of the Avalon-MM address space, and only needs a 25-bit wide address bus, leaving space for other Avalon-MM slaves.
Table 12.  Write address mapping table (Offset 16’h0200)The Write address mapping table is 32 locations and 64bit wide each.
Bit[63:0] Name R/W Default Description
[63:0] WAdm R/W 0 This register contains the Traffic Generator address mapping table that maps thirty-two 1 MB regions of the Avalon-MM memory space into thirty-two 1 MB regions of the PCIe address space. The module occupies only 32MB of the Avalon-MM address space, and only needs a 25-bit wide address bus, leaving space for other Avalon-MM slaves.

Did you find the information on this page useful?

Characters remaining:

Feedback Message