Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 2/06/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.5. Running the Design Example Application on a Hardware Setup

The following list details the development kits used for testing:
  • Intel® Stratix® 10 GX/MX devices using the H-Tile PCIe Gen3 hard IP
  • Intel® Stratix® 10 DX
  • Intel® Agilex™ devices using the P-Tile PCIe Gen4 Hard IP and soft IP