Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 2/06/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.1.1.2. Hardware Test Result

The Custom Driver and DPDK Driver were used to generate the following output:
Figure 4. PIO Test-o option