Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 2/06/2022

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Document Table of Contents BAM Test

If the BAM support is enabled on hardware, enable the following flag in common/mk/

__cflags += -DIFC_PIO_256 → 256b read/write operations on PIO BAR

__cflags += -DIFC_PIO_128 → 128b read/write operations on PIO BAR

To enable 256b read/write operations, this is the difference in
Command: ./cli/perfq_app/perfq_app -b 0000:86:00.0 -o
To enable 128b read/write operations:

To test the PIO/BAM performance, please use the following command:

./perfq_app -b 0000:01:00.0 --bam_perf -o

[root@bapvemb005t perfq_app]# ./perfq_app -b 0000:01:00.0 --bam_perf -o
PIO 64 Write and Read Perf Test ...
Total Bandwidth:                0.14GBPS
[root@bapvemb005t perfq_app]#
  • By default BAM/BAS, BAR is 2. If DMA HW supports both BAM/BAS and BAR numbers are different, then pass BAR number parameter as below:

    --bar=2 for BAM

    --bar=0 for BAS

  • For example:
    ./perfq_app -b 0000:01:00.0 --bam_perf -o --bar=2
  • PIO 256b test may display fail because of the reason that 2k memory only enabled in device and PIO test trying to access the memory > 2k