2.3.2. Avalon-MM PIO Using MCDMA Bypass mode
This design example enables Avalon-MM PIO master which bypasses the DMA path. The Avalon-MM PIO master allows application to perform single, non-bursting register read/write operation with on-chip memory.
This design example only supports PIO functionality and does not perform DMA operations (similar to the design examples in Avalon-ST PIO Using MCDMA Bypass Mode). Hence, the Avalon-MM DMA ports are not connected.
- resetIP – Reset Release IP that holds the Multi Channel DMA in reset until the entire FPGA fabric enters user mode.
- MEM_PIO – On-chip memory for the PIO operation. Connected to the MCDMA Avalon-MM PIO Master (rx_pio_master) port that is mapped to PCIe BAR2.
- PIO test: -o
For a description of which driver(s) to use with this design example, refer to Driver Support.
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