Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 2/06/2022
Public

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2.6.2. Hardware Test Results

The Custom Driver, DPDK Driver, and Kernel Mode Driver were used to generate the following output:
Figure 30. PIO Test-o option
Figure 31. H2D Avalon-MM Write-t option. Note: This hardware test was run with the Intel® Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
Figure 32. H2D Avalon-MM Write with Data Validation Enabled-t -v option. Note: This hardware test was run with the Intel® Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
Figure 33. D2H Avalon-MM Read-r option. Note: This hardware test was run with the Intel® Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.

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