Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 2/06/2022
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2.4.1.1. Simulation Results

Note: For detailed description about the testbench for this design example, refer to Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example.
Figure 11. H2D Simulation Log
Figure 12. H2D Simulation Waveform
Figure 13. D2H Simulation Log
Figure 14. D2H Simulation Waveform