Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 2/06/2022
Public

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2.8.1.1. GCSR Registers (Base address 64’h00000)

Table 15.  Revision Register (Offset 8’h00)
Bit[63:0] Name R/W Default Description
[63:0] revision R0 1 Read-only revision number.
Table 16.  Soft-reset Register (Offset 8’h08)
Bit[63:0] Name R/W Default Description
[63:1] rsvd Reserved
[0:0] Soft_reset R/W 0 Soft-reset register to reset the QCSR block, Software needs to write 1 to reset and then write 0 to un-reset.

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