Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 2/06/2022

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Document Table of Contents

5. Document Revision History for the Multi Channel DMA for FPGA IP Design Example User Guide

Date Intel® Quartus® Prime Version IP Version Changes
2022.02.06 21.4

H-Tile IP version: 21.3.0

P-Tile IP version: 2.2.0

F-Tile IP version: 1.1.0

  • Added new design example: External Descriptor Controller
  • Added information for the Traffic Generator/Checker example design in
2021.12.01 21.3

H-Tile IP version: 21.2.0

P-Tile IP version: 2.1.0

F-Tile IP version: 1.0.0

Rev H-Tile 21.2.0—2K channel support for D2H

Rev P-Tile 2.1.0—CS address width reduced from 29 to 14 bits

Rev F-Tile 1.0.0:
  • F-Tile support added
  • BAS EP design example added

Added new design example: Traffic Generator/Tracker

2021.09.15 21.2

H-Tile: 21.1.0

P-Tile: 2.0.0

  • Added SRIOV support for DPDK PMD
  • Added support for kernel mode driver
  • Added the Multi Channel DMA for FPGA IP Design Example User Guide Archives section
2021.05.24 21.1

H-tile: 2.0.0

P-tile: 1.0.0

  • Added the single-port Avalon-ST design example
  • Added support for new BAM, BAS, BAM+BAS, and BAM+MCDMA user modes
  • Added support for the DPDK PMD driver
  • Added support for the Xcelium simulator
2020.08.05 20.2

H-tile: 20.0.0

Initial Release