R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/10/2024
Document Table of Contents

4.3. PCI Express Mode

In PCI Express mode, only the PCI Express controller stack is active. The four PCI Express cores (x16, x8, x4_0 and x4_1) interface with the application logic in the FPGA fabric via Avalon® streaming interfaces. You can determine which core each interface in this section belongs to by looking at the prefixes in the signal names:
  • p0 : x16 core
  • p1 : x8 core
  • p2 : x4_0 core
  • p3 : x4_1 core
The x4_0 core is only available in Production devices or Engineering Samples with the following OPNs:
  • AGIx027R29AxxxxR2
  • AGIx027R29AxxxxR3
  • AGIx027R29BxxxxR3
  • AGIx023R18AxxxxR0
  • AGIx041R29DxxxxR0
  • AGIx041R29DxxxxR1
  • AGMx039R47AxxR0
For additional details on OPN decoding, refer to the Available Options section of the Agilex™ 7 FPGAs and SoCs Device Overview.

R-Tile Top-Level Block Diagram in PCI Express Mode below shows the top-level signals of this IP. Note that the signal names in the figure will get the appropriate prefixes pn (where n = 0, 1, 2 or 3) depending on which of the supported topologies (x16, x8x8, x4x4x4x4) the R-Tile Avalon® streaming Intel FPGA IP for PCIe is in.

The only cases where the interface signal names do not get the pn prefixes are the interfaces that are common for all the cores, like clocks and resets.

Figure 25. R-Tile Top-Level Block Diagram in PCI Express Mode

pX: X is port number, ranges from 0 to 3.

stN: N is segment number, ranges from 0 to 3.