R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/10/2024
Document Table of Contents Transmit Signals

Table 80.  PIPE Direct EMIB Data Channel Transmit SignalsIn the signal names, X is the lane number and ranges from 0 to 15.
Signal Name Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_txelecidle_i[3:0] Input One bit per two Symbols, for a maximum of 8 symbols. The PHY will mask off the txdata as long as txelecidle is asserted. As per the PHY Interface for PCI Express Specification, Version 5.1.1, the txdatavalid signal must be asserted whenever txelecidle toggles. 1 bit of txelecidle is required per 16 bits of data. Refer to section 8.19 of the PIPE specification for more details. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_txdatavalid1_i Input This signal qualifies txdata[63:32]. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_txdatavalid0_i Input This signal qualifies txdata[31:0]. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_txdata_i[63:0] Input Transmit data bus pipe_direct_pld_tx_clk_out_o

The following timing diagrams provide an illustration of the behaviors of the PIPE Direct TX Datapath signals:

Figure 43. PIPE Direct TX Datapath
Note: At Gen1 and Gen2 speeds, only the 10 LSB bits from the lower segment of LnX_pipe_direct_txdata bus contain valid data. Bits [63:10] are don't-cares.