R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/10/2024
Document Table of Contents

E.3.1. Debug Toolkit Testing Process

As previously mentioned, Intel recommends you to perform the procedure detailed in 5x5 Testing Efficiency, where you test five different boards with five power-cycled runs on each part or board. This is the recommended process:
  1. Power on the board with the link under test at the L0 LTSSM state and at the desired PCIe Speed with no recoveries on the PCIe link.
  2. Load the Debug Toolkit and run the Lane Margining tool to get the margins on all PCIe lanes and store the data samples.
  3. Apply a power cycle to the board and repeat steps 1 and 2 five times once the PCIe link under test is properly trained.
  4. Perform steps 1 to 3 for each test board (in this case five different boards or parts).
  5. Finally, you must get an average of the collected Time Margin, Voltage Margin Up and Voltage Margin Down values to compare with Margin Mask values provided in Margin Mask Values for the R-Tile Avalon Streaming Intel FPGA IP for PCI Express. If any average value of the lane margins is greater than or equal to the Margin Mask value, it means that the test values are good and meet the minimum values required. Otherwise, if the value of the average lane margins is less than the Margin Mask value, it means that there are more CRC errors than expected and the link has not been trained correctly.