R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/10/2024
Document Table of Contents Channel Parameters

The Channel Parameters window allows you to read the transmitter and receiver settings for a given channel. It has the following 4 sub-windows.
  • General PHY
  • Tx Path
  • Rx Path
  • Lane Margining

Use the Lane Refresh button to read the status of the General PHY, TX Path, and RX Path sub-windows for each channel.

The Channel Parameters tab is only available in Production devices or Engineering Samples with the following OPNs:
  • AGIx027R29AxxxxR2
  • AGIx027R29AxxxxR3
  • AGIx027R29BxxxxR3
  • AGIx023R18AxxxxR0
  • AGIx041R29DxxxxR0
  • AGIx041R29DxxxxR1
  • AGMx039R47AxxR0
For additional details on OPN decoding, refer to the Available Options section of the Agilex™ 7 FPGAs and SoCs Device Overview.
Note: To refresh channel parameters for more than one lane simultaneously, select the lanes under the Collection tab, right click and select Refresh.
Note: The per-lane information under the Channel Parameters tab corresponds to the physical lanes.
Figure 69.  Channel Parameters Tab Showing 3 Lanes Selected with the Menu to be Refreshed

You can use the Columns drop down menu, the Column width and the Row height bars to adjust the graphical interface when monitoring multiple lanes at the same time.

Figure 70. Parameters to Adjust the Graphical Interface