R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/10/2024
Document Table of Contents Malformed TLP

In TLP Bypass mode, a malformed TLP is dropped in the R-Tile IP for PCIe and its event is logged in the AER capability registers. R-Tile also notifies you of this event by asserting the serr_out_o signal.

Refer to the PCI Express Base Specification for the definition of a malformed TLP.