R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/10/2024
Document Table of Contents VirtIO Supported Features List

  • VirtIO devices are implemented as PCI Express devices.
  • Support 8 PFs and 2K VFs VirtIO capability structure.
    • For Port 2 and Port 3, VirtIO is only supported in Production devices or Engineering Samples with the following OPNs:
      • AGIx027R29AxxxxR2
      • AGIx027R29AxxxxR3
      • AGIx027R29BxxxxR3
      • AGIx023R18AxxxxR0
      • AGIx041R29DxxxxR0
      • AGIx041R29DxxxxR1
      • AGMx039R47AxxR0
      For additional details on OPN decoding, refer to the Available Options section of the Agilex™ 7 FPGAs and SoCs Device Overview.
  • Configuration Intercept Interface in the R-Tile IP for PCIe (EP mode only) is provided for VirtIO transport.
  • Five VirtIO device configuration structures are supported:
    • Common configuration
    • Notifications
    • ISR Status
    • Device-specific configuration (optional)
    • PCI configuration access
  • Location of each structure is specified using a vendor-specific PCI capability located in the PCI configuration space of the device.
  • VirtIO capability structure uses little-endian format.
  • All fields of the VirtIO capability structure are read-only for the driver by default.
  • Support PFs and VFs FLR
    Note: The Read/Write registers in the VF and PF VirtIO capability registers are not reset by FLR.
  • Supports x16 and x8 cores.
  • MSI is not supported with VirtIO.
    Note: In the 22.1 release of Quartus® Prime, when you enable the VirtIO feature, all the PFs in the Hard IP must support VirtIO. The configuration where some PFs support VirtIO and some PFs support MSI is not available.