R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/10/2024
Document Table of Contents REFCLK and PERST Guidelines When Using Independent PERST Pins

In Configuration Mode 1 (2x8 Endpoint only), the independent PERST and REFCLK are available with:
  • The IP parameter Enable Independent Perst pins set to enabled.
  • The clock source for refclk2 must be always running.
  • refclk2 does not require a specific Quartus Setting File assignment for its pin location. You must not make a specific location assignment for this pin. The Quartus® Prime software tool selects the corresponding pin location based on the location assignments made for the rest of the R-Tile pins.
  • The pin_perst_n pin must qualify the stability of refclk2.
  • The pin_perst_n pin has the highest priority and toggling it affects both Port 0 and Port 1.
  • For Port 0 (P0):
    • The clock source comes from refclk0.
    • The reset source can come from pin_perst0_n at the package level or p0_warm_perst_n_i.
  • For Port 1 (P1):
    • The clock source comes from refclk1.
    • The reset source can come from pin_perst1_n at the package level or p1_warm_perst_n_i.