R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/10/2024
Document Table of Contents Lane Margining

The R-Tile Debug Toolkit supports electrical lane margining that allows you to assess the electrical health for each channel. This feature allows you to:
  • Assess the voltage margin (vertical) from sampling point to top and bottom.
  • Assess the time margin (horizontal) from sampling point to left and right. However, please note that the R-Tile Debug Toolkit will only report the minor margin measured between the left margin and the right margin.
  • Perform lane margining with the following configurations:
    • Configuration Mode 0 (1x16) and Configuration Mode 1 (2x8)
    • 8.0 GT/s (PCIe 3.0) at BER 10e-9
    • 16.0 GT/s (PCIe 3.0) at BER 10e-9
    • 32.0 GT/s (PCIe 3.0) at BER 10e-9
  • Perform automatic comparison of lane margining results versus the reference mask at BER 10e-9 and BER 10e-12. The lane margining exercise is performed at a BER of 10e-9. However, the tool automatically compares the results against the recommended mask for both BER 10e-9 and BER 10e-12.
Note: Intel recommends that the margin for each lane on your board be more than the mask in the horizontal and vertical directions to make sure that the channel is good and meets the PCIe specification. For more information on the Margin Masks, refer to Margin Masks for the R-Tile Avalon Streaming Intel FPGA IP for PCI Express.
Note: The R-Tile Avalon Streaming Intel FPGA IP for PCI Express Lane Margining feature of the Debug Toolkit does not support an independent error sampler for performing the lane margining. The lane margining is performed on the actual data path. As a result, the lane margining may produce uncorrectable errors in the data stream and cause the Link Training and Status State Machine (LTSSM) to go into the Recovery state. You may mask out all errors through the Advanced Error Reporting (AER) registers while performing lane margining, and reset all error counters, error registers, etc. after margining completes.
Figure 74. Lane Margining
Execute the following procedure to perform lane margining for a given lane:
  1. Select the targeted lane on the Collection tab.

  2. A new panel is displayed on the Channel Parameters tab. Select the Lane Margining sub-tab.
  3. Under the Lane Margin section, select Time Margin (Horizontal) and/or Voltage Margin (Vertical).
  4. Under the Lane Margining Results section, click the Start button. Alternatively, you can right-click on the targeted lane and select Start Lane Margining.

  5. The lane margining may take several minutes to complete. Wait until the results are displayed.

  6. Once the lane margining results are available, the Debug Toolkit automatically compares them against the recommended Masks and provides a comparison result by printing Above Mask or Below Mask. This label appears next to the mask values. Refer to Margin Masks for the R-Tile Avalon Streaming Intel FPGA IP for PCI Express for details on the suggested methodology to evaluate your overall link margins.
    Note: The Debug Toolkit reports Above Mask if the obtained margin is above the BER 10e-9 mask but less than the BER 10e-12 mask.