R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/10/2024
Document Table of Contents

2.3. PIPE Direct Mode

In PIPE Direct mode, application logic is responsible for implementing the Transaction Layer, Data Link Layer and the logic PHY/MAC (including the 8b/10b, 128b/130b Encoder/Decoder, Elastic Buffer, Link Training and Status State Machine (LTSSM), etc.) in your application logic in the FPGA fabric. Note that in PIPE Direct mode, R-Tile implements the SerDes Architecture mode, and the PCS responsibilities must be implemented in the Soft IP logic PHY/MAC layer. Only the PMA layer inside the R-Tile IP for PCIe is active as shown in the following figure.

Note: When implementing a Soft IP Controller using the R-Tile IP for PCI Express in PIPE Direct mode, the FPGA device must be fully configured in order to start the link training sequence since the Controller is in the FPGA fabric.
Figure 15. PIPE Direct Mode Top-Level Block Diagram