R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/10/2024
Document Table of Contents

4.1.1. Clocks

Table 45.  Clocks
Name Direction Description EP/RP/BP/PIPE-D Clock Frequency
coreclkout_hip Output This clock drives the Data Link, Transaction, and Application Layers. For the Application Layer, the frequency depends on the data rate and the number of lanes as specified. EP/RP/BP

Native Gen5: 400/425/450/475/500 MHz

Native Gen4: 250/275/300 MHz

Native Gen3: 250/275/300 MHz

The frequency can change depending on whether the IP is operating in single-width or double-width mode.

Note: Single-width mode is not supported in the 21.4 release of Quartus® Prime.
refclk0, refclk1, refclk2 Input

These are the input reference clocks for the IP core. They must be free-running clocks. You may experience an error while reconfiguring or performing a CvP Update operation on your device if there is no stable free-running clock.

These reference clocks are not available to the FPGA user logic. The only clocks available to the user logic from R-Tile are coreclkout_hip, slow_clk in the PCIe mode, and pipe_direct_pld_tx_clk_out_o and LnX_pipe_direct_pld_rx_clk_out_o in the PIPE mode.

Note: When using the Agilex™ 7 AGI041 device, the refclk2 input port does not require a specific Quartus Setting File assignment for its pin location. You must not make a specific location assignment for this pin. The Quartus® Prime software tool selects the corresponding pin location based on the location assignments made for the rest of the R-Tile pins.
EP/RP/BP/PIPE-D 100 MHz ± 100 ppm
Note: For Gen5-capable systems, the clock frequency is 100 MHz ± 100 ppm
reconfig_clk Input This clock is required for proper speed change operation in PIPE Direct mode. PIPE-D

100 MHz (Recommended)

50 MHz - 125 MHz (Permitted Range)

slow_clk Output This is the clock for sideband signals. EP/RP/BP

Divide-by-2 or divide-by-4 clock derived from coreclkout_hip. Use the Slow Clock Divider option in the Parameter Editor to choose between the divide-by-2 or divide-by-4 versions of coreclkout_hip for this clock.

pipe_direct_pld_tx_clk_out_o Output This is the TX clock for the PIPE Direct mode. PIPE-D 500 MHz

(X is the lane number and ranges from 0 to 15. There is one clock output per lane.)

Output This is the RX clock for the PIPE Direct mode. It is the per-lane CDR recovery clock. PIPE-D The clock frequency depends on the lane rate (Gen1 to Gen5).
  • Gen1 = 125 MHz
  • Gen2 = 250 MHz
  • Gen3 = 125 MHz
  • Gen4 = 250 MHz
  • Gen5 = 500 MHz