R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/10/2023

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4.4.3. Message Bus Signals

This interface is used for PHY (P)-MAC (M) communication, using the P2M and M2P unidirectional 8-bit signals per lane. This interface serves to reduce the number of dedicated signals for implementations like link equalization, lane margining etc.

Table 84.  PIPE Direct EMIB Control Message Channel M2P/P2M Signals
Signal Name Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_m2p_messagebus_i[7:0] Input Low Pin Count Message Interface from MAC to PHY. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_p2m_messagebus_o[7:0] Output Low Pin Count Message Interface from PHY to MAC. pipe_direct_pld_tx_clk_out_o
The R-tile in PIPE Direct mode does not support querying the FS/LS/Preset/Coefficient values via the PIPE interface. In addition, EQ feedback direction is not supported. Only the Figure of Merit (FOM) must be implemented using the following values:
  • For the OPNs AGIx027R29AxxxxR0, AGIx027R29AxxxxR1:
    • For Gen3/Gen4/Gen5: FS = 48, LF = 16
    • For Gen3/Gen5:

      {c-1, c0, c+1 = preset} = {8/40/0 = P9}

    • For Gen4:

      {c-1, c0, c+1 = preset} = {0/42/6 = P3}

  • For the OPNs AGIx027R29AxxxxR2, AGIx027R29AxxxxR3, AGIx027R29BxxxxR3, AGIx023R18AxxxxR0, AGIx041R29DxxxxR0, AGIx041R29DxxxxR1:
    • For Gen3/Gen4/Gen5: FS = 48, LF = 16
    • For Gen5:

      {c-1, c0, c+1 = preset} = {6/36/6 = P8}

      {c-1, c0, c+1 = preset} = {8/40/0 = P9}

    • For Gen4:

      {c-1, c0, c+1 = preset} = {0/42/6 = P3}

      {c-1, c0, c+1 = preset} = {5/33/10 = P7}

    • For Gen3:

      {c-1, c0, c+1 = preset} = {0/48/0 = P4}

For additional details on OPN decoding, refer to the Available Options section of the Intel Agilex® 7 FPGAs and SoCs Device Overview.

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