|coreclkout_hip||Output||This clock drives the Data Link, Transaction, and Application Layers. For the Application Layer, the frequency depends on the data rate and the number of lanes as specified.||EP/RP/BP||
Native Gen5: 400/425/450/475/500 MHz
Native Gen4: 250/275/300 MHz
Native Gen3: 250/275/300 MHz
The frequency can change depending on whether the IP is operating in single-width or double-width mode.
Note: Single-width mode is not supported in the 21.4 release of Intel® Quartus® Prime.
These are the input reference clocks for the IP core. They must be free-running clocks. You may experience an error while reconfiguring or performing a CvP Update operation on your device if there is no stable free-running clock.
These reference clocks are not available to the FPGA user logic. The only clocks available to the user logic from R-tile are coreclkout_hip, slow_clk in the PCIe mode, and pipe_direct_pld_tx_clk_out_o and LnX_pipe_direct_pld_rx_clk_out_o in the PIPE mode.
|EP/RP/BP||100 MHz ± 100 ppm
Note: For Gen5-capable systems, the clock frequency is 100 MHz ± 100 ppm
|reconfig_clk||Input||This clock is required for proper speed change operation in PIPE Direct mode.||PIPE-D||
100 MHz (Recommended)
50 MHz - 125 MHz (Permitted Range)
|slow_clk||Output||This is the clock for sideband signals.||EP/RP/BP||
Divide-by-2 or divide-by-4 clock derived from coreclkout_hip. Use the Slow Clock Divider option in the Parameter Editor to choose between the divide-by-2 or divide-by-4 versions of coreclkout_hip for this clock.
|pipe_direct_pld_tx_clk_out_o||Output||This is the TX clock for the PIPE Direct mode.||PIPE-D||500 MHz|
(X is the lane number and ranges from 0 to 15. There is one clock output per lane.)
|Output||This is the RX clock for the PIPE Direct mode. It is the per-lane CDR recovery clock.||PIPE-D||The clock frequency depends on the lane rate (Gen1 to Gen5).