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1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
2. IP Architecture and Functional Description
3. Advanced Features
4. Interfaces
5. Parameters
6. Troubleshooting/Debugging
7. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide Archives
8. Document Revision History for the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode
E. Margin Masks for the R-Tile Avalon Streaming Intel FPGA IP for PCI Express
3.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012)
3.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013)
3.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014)
3.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015)
3.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016)
3.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017)
3.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018)
3.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019)
3.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A)
3.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F)
3.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030)
3.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031)
3.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032)
3.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033)
3.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034)
3.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035)
3.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036)
3.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037)
3.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038)
3.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039)
3.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A)
3.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
4.3.1. Avalon® Streaming Interface
4.3.2. Precision Time Measurement (PTM) Interface (Endpoint Only)
4.3.3. Interrupt Interface
4.3.4. Hard IP Reconfiguration Interface
4.3.5. Error Interface
4.3.6. Completion Timeout Interface
4.3.7. Configuration Intercept Interface
4.3.8. Power Management Interface
4.3.9. Hard IP Status Interface
4.3.10. Page Request Services (PRS) Interface (Endpoint Only)
4.3.11. Function-Level Reset (FLR) Interface (Endpoint Only)
4.3.12. SR-IOV VF Error Flag Interface (Endpoint Only)
4.3.13. General Purpose VSEC Interface
5.2.3.1. Device Capabilities
5.2.3.2. VirtIO Parameters
5.2.3.3. Link Capabilities
5.2.3.4. Legacy Interrupt Pin Register
5.2.3.5. MSI Capabilities
5.2.3.6. MSI-X Capabilities
5.2.3.7. Slot Capabilities
5.2.3.8. Latency Tolerance Reporting (LTR)
5.2.3.9. Process Address Space ID (PASID)
5.2.3.10. Device Serial Number Capability
5.2.3.11. Page Request Service (PRS)
5.2.3.12. Access Control Service (ACS)
5.2.3.13. Power Management
5.2.3.14. Vendor Specific Extended Capability (VSEC) Registers
5.2.3.15. TLP Processing Hints (TPH)
5.2.3.16. Address Translation Services (ATS) Capabilities
5.2.3.17. Precision Time Management (PTM)
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1.2. Features
The R-tile Avalon® streaming Intel FPGA IP for PCI Express* supports the following features:
- Includes a complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as a Hard IP.
- Supports Root Port (RP), Endpoint (EP) and TLP Bypass (BP) modes.
Table 2. Configurations Natively Supported by R-tileEndpoint = EP; Root Port = RP; TLP Bypass = BP Configuration Application Interface Data Width (bits) EP/RP/BP Gen5/Gen4/Gen3 x16 1024 EP/RP/BP Gen4/Gen3 x16 512 1 EP/RP/BP Gen5/Gen4/Gen3 x8x8 512 EP/RP/BP Gen4/Gen3 x8x8 256 1 EP/RP/BP Gen5/Gen4/Gen3 x4x4x4x4 256 EP/RP/BP Gen4/Gen3 x4x4x4x4 128 1 EP/RP/BP PIPE Direct 64 bits per Lane N/A Note: Gen1/Gen2 configurations are supported via link down-training. -
Table 3. Topologies Supported by R-tile Topology\ Lane# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x16 Port 0 (EP/RP/BP) x8x8 Port 0 (EP/RP/BP) Port 1 (EP/RP/BP) x4x4x4x4 Port 2 (EP/RP/BP) Port 0 (EP/RP/BP) Port 1 (EP/RP/BP) Port 3 (EP/RP/BP) PIPE Direct PIPE Direct Note:Port 2 is only available in the following OPNs:- AGIx027R29AxxxxR2
- AGIx027R29AxxxxR3
- AGIx027R29BxxxxR3
- AGIx023R18AxxxxR0
- AGIx041R29DxxxxR0
- AGIx041R29DxxxxR1
- The following PIPE Direct bundle modes are supported and are selectable via the PIPE Direct Mode menu in the Parameter Editor in Intel® Quartus® Prime:
- 1x16
- 2x8
- 4x4
- 8x2
- 16x1
- 2x4 : 1x8
- 4x2 : 1x8
- 8x1 : 1x8
- 1x8 : 2x4
- 4x2 : 2x4
- 8x1 : 2x4
- 1x8 : 4x2
- 2x4 : 4x2
- 8x1 : 4x2
- 1x8 : 8x1
- 2x4 : 8x1
- 4x2 : 8x1
Note: 1x16 means all 16 PIPE Direct channels act in a bundle mode. 16x1 means all 16 channels act as independent channels. 2x8 means the channels are in two 8-channel bundles. 2x4 : 1x8 means the channels in the Lower 8 lanes are organized as two 4-channel bundles, while the channels in the Upper 8 lanes are in an 8-channel bundle. Refer to PIPE Direct Reset Sequence for reset considerations when lanes 0-8 are not in use by the Soft IP Controller. - Static port bifurcation (x8x8, x4x4x4).
- Supports Precision Time Management (PTM) (Endpoint only).
Note: Only Ports 0 and 1 support PTM.
- Supports TLP Bypass mode in Upstream or Downstream configuration.
- Supports one x16, two x8, or four x4 interfaces.
- Supports up to 512-byte maximum payload size (MPS).
- Supports up to 4096-byte (4 KB) maximum read request size (MRRS).
- Single Virtual Channel (VC).
- Latency Tolerance Reporting (LTR).
- Page Request Services (PRS).
Note: Only Ports 0 and 1 support PRS.
- MSI and MSI-X.
Note: Only Ports 0 and 1 support MSI and MSI-X.
- Completion Timeout Ranges.
- Atomic Operations (FetchAdd/Swap/CAS).
- Extended Tag Support.
- 10-bit Tag Support (Maximum of 768 outstanding tags (x16) / 512 outstanding tags (x8/x4) at any given time, for all functions combined).
- Separate Refclk with Independent Spread Spectrum Clocking (SRIS).
- Separate Refclk with no Spread Spectrum Clocking (SRNS).
- Common Refclk architecture.
- PCI Express* Advanced Error Reporting (PF only).
Note: Advanced Error Reporting is always enabled in the R-tile Avalon® streaming Intel FPGA IP for PCIe.
- ECRC generation and checking (when the IP is not in TLP Bypass mode).
- Application logic needs to handle ECRC generation and checking when the IP is in TLP Bypass mode.
- Data bus parity protection.
- Supports D0 and D3 device power management states.
- Lane Margining at Receiver.
- Retimers presence detection.
- User packet interface with separate header, data and prefix.
- User packet interface with a split-bus architecture where the header, data and prefix busses consist of four segments each (x16 mode only).
- Up to 768 outstanding Non-Posted requests (x16 core only).
- Up to 512 outstanding Non-Posted requests (x8 and x4 cores).
- Summary of outstanding Non-Posted requests supported when 8-bit tags or 10-bit tags are enabled:
Table 4. Outstanding Non-Posted Requests Supported Ports Active Cores 8-bit Tags 10-bit Tags 0 x16 256 768 (*) 1 x8 256 512 2 and 3 x4 256 512 Note: (*): Use tags 256 to 1023. - Completion timeout interface.
- The PCIe Hard IP can optionally track outgoing non-posted packets to report completion timeout information to the application.
- You cannot change the pin allocations for the R-tile Avalon® streaming Intel FPGA IP for PCI Express* in the Intel® Quartus® Prime project. However, this IP does support lane reversal per port (x16, x8, x4_0, x4_1) and polarity inversion on the PCB by default.
- Supports Autonomous Hard IP mode.
- This mode allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into User mode are complete.
Note: Unless Readiness Notifications mechanisms are used, the Root Complex or the system software must allow at least one second after a Conventional Reset of a device before it may determine that a device that fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training completes.
- This mode allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into User mode are complete.
- Supports CvP Init and CvP Update.
Note: For Gen3, Gen4 and Gen5 x16 variants, Port 0 (corresponding to lanes 0 - 15) supports the CvP features. For Gen3, Gen4 and Gen5 x8 variants, only Port 0 (corresponding to lanes 0 - 7) supports the CvP features. Port 1 (corresponding to lanes 8 - 15) does not support CvP.
- VCS*, VCS* MX, Siemens EDA QuestaSim*, and Xcelium* are the only simulators supported in the 23.1 release of Intel® Quartus® Prime.
Note:The Xcelium* simulator support is only available in the following OPNs:For more details on OPN decoding, refer to the Available Options section of the Intel Agilex® 7 FPGAs and SoCs Device Overview.
- AGIx027R29AxxxxR2
- AGIx027R29AxxxxR3
- AGIx027R29BxxxxR3
- AGIx023R18AxxxxR0
- AGIx041R29DxxxxR0
- AGIx041R29DxxxxR1
- The R-tile PHY layer does not support sending a Beacon signal.
Note: Throughout this User Guide, the term Avalon-ST may be used as an abbreviation for the Avalon® streaming interface or IP.
1 These configurations are only available in the following OPNs: AGIx027R29AxxxxR2, AGIx027R29AxxxxR3, AGIx027R29BxxxxR3, AGIx023R18AxxxxR0, AGIx041R29DxxxxR0, AGIx041R29DxxxxR1. For more details on OPN decoding, refer to the Available Options section of the Intel Agilex® 7 FPGAs and SoCs Device Overview