188.8.131.52.2. Avalon® Streaming TX Interface pX_tx_st_ready_o Behavior
The following timing diagram illustrates the behavior of pX_tx_st_ready_o, which is deasserted to pause the data transmission to the R-tile PCI Express IP core, and then reasserted. The application logic deasserts pX_tx_stN_valid_i 16 clock cycles after pX_tx_st_ready_o is deasserted (from the point marked with the letter a to the point marked with the letter b). This is the maximum number of clock cycles allowed between the deassertion of pX_tx_st_ready_o and pX_tx_stN_valid_i.
When the R-Tile PCI Express IP Core reasserts the pX_tx_st_ready_o signal (point marked with letter c to point marked with letter d), the following two cases must be considered:
Case 1: If there is a TLP suspended due to the deassertion of pX_tx_st_ready_o, then the maximun number of clock cycles for pX_tx_stN_valid_i to go high after the assertion of pX_tx_st_ready_o is one (as illustrated in the following figure).
Case 2: If there is no TLP suspended due to the deassertion of pX_tx_st_ready_o, then there is no requirement, and the application logic can reassert pX_tx_stN_valid_i as soon as it has a TLP available to transmit.
The application must not deassert pX_tx_stN_valid_i between pX_tx_stN_sop_i and pX_tx_stN_eop_i unless there is backpressure from the R-tile PCIe IP indicated by the deassertion of pX_tx_st_ready_o.