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1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
2. IP Architecture and Functional Description
3. Advanced Features
4. Interfaces
5. Parameters
6. Troubleshooting/Debugging
7. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide Archives
8. Document Revision History for the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode
E. Margin Masks for the R-Tile Avalon Streaming Intel FPGA IP for PCI Express
3.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012)
3.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013)
3.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014)
3.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015)
3.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016)
3.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017)
3.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018)
3.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019)
3.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A)
3.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F)
3.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030)
3.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031)
3.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032)
3.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033)
3.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034)
3.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035)
3.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036)
3.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037)
3.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038)
3.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039)
3.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A)
3.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
4.3.1. Avalon® Streaming Interface
4.3.2. Precision Time Measurement (PTM) Interface (Endpoint Only)
4.3.3. Interrupt Interface
4.3.4. Hard IP Reconfiguration Interface
4.3.5. Error Interface
4.3.6. Completion Timeout Interface
4.3.7. Configuration Intercept Interface
4.3.8. Power Management Interface
4.3.9. Hard IP Status Interface
4.3.10. Page Request Services (PRS) Interface (Endpoint Only)
4.3.11. Function-Level Reset (FLR) Interface (Endpoint Only)
4.3.12. SR-IOV VF Error Flag Interface (Endpoint Only)
4.3.13. General Purpose VSEC Interface
5.2.3.1. Device Capabilities
5.2.3.2. VirtIO Parameters
5.2.3.3. Link Capabilities
5.2.3.4. Legacy Interrupt Pin Register
5.2.3.5. MSI Capabilities
5.2.3.6. MSI-X Capabilities
5.2.3.7. Slot Capabilities
5.2.3.8. Latency Tolerance Reporting (LTR)
5.2.3.9. Process Address Space ID (PASID)
5.2.3.10. Device Serial Number Capability
5.2.3.11. Page Request Service (PRS)
5.2.3.12. Access Control Service (ACS)
5.2.3.13. Power Management
5.2.3.14. Vendor Specific Extended Capability (VSEC) Registers
5.2.3.15. TLP Processing Hints (TPH)
5.2.3.16. Address Translation Services (ATS) Capabilities
5.2.3.17. Precision Time Management (PTM)
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3.3.2.1. TLPBYPASS_ERR_EN (Address 0x1314)
This register allows you to enable or disable error reporting. When this feature is disabled, the TLPBYPASS_ERR_ STATUS bit associated with an error is not set when the error is detected.
Name | Bits | Reset Value | Access Mode | Register Description |
---|---|---|---|---|
Reserved | [31:20] | 12’b0 | RO | Reserved |
k_cfg_uncor_internal_err_sts_en | [19] | 1'b1 | RW | Enable error indication on serr_out_o for Uncorrectable Internal Error. |
k_cfg_corrected_internal_err_sts_en | [18] | 1'b1 | RW | Enable error indication on serr_out_o for Corrected Internal Error. |
k_cfg_rcvr_overflow_err_sts_en | [17] | 1'b1 | RW | Enable error indication on serr_out_o for Receiver Overflow Error. |
k_cfg_fc_protocol_err_sts_en | [16] | 1'b1 | RW | Enable error indication on serr_out_o for Flow Control Protocol Error. |
k_cfg_mlf_tlp_err_sts_en | [15] | 1'b1 | RW | Enable error indication on serr_out_o for Malformed TLP Error. |
k_cfg_surprise_down_err_sts_en | [14] | 1'b1 | RW | Enable error indication on serr_out_o for Surprise Down Error. |
k_cfg_dl_protocol_err_sts_en | [13] | 1'b1 | RW | Enable error indication on serr_out_o for Data Link Protocol Error. |
k_cfg_replay_number_rollover_err_sts_en | [12] | 1'b1 | RW | Enable error indication on serr_out_o for REPLAY_NUM Rollover Error. |
k_cfg_replay_timer_timeout_err_st_en | [11] | 1'b1 | RW | Enable error indication on serr_out_o for Replay Timer Timeout Error. |
k_cfg_bad_dllp_err_sts_en | [10] | 1'b1 | RW | Enable error indication on serr_out_o for Bad DLLP Error. |
k_cfg_bad_tlp_err_sts_en | [9] | 1'b1 | RW | Enable error indication on serr_out_o for Bad TLP Error. |
k_cfg_rcvr_err_sts_en | [8] | 1'b1 | RW | Enable error indication on serr_out_o for Receiver Error. |
Reserved | [7:1] | 7'b0 | RO | Reserved |
k_cfg_ecrc_err_sts_en | [0] | 1'b1 | RW | Enable error indication on serr_out_o for ECRC Error. |