3.3.3. Hard IP Reconfiguration Interface
For more details on the signals in this interface, refer to the section Hard IP Reconfiguration Interface.
The majority of the PCIe standard capability structures are implemented in the application logic outside of the R-tile Avalon® -ST IP.
- Power management capability structure
- A portion of the PCI Express capability structure is implemented inside R-tile. However, the following registers within this structure still need to be implemented by the application logic:
- PCI Express Capability List register
- PCI Express Capabilities register
- Device Capabilities register
- Device Control register
- Device Status register
- Secondary PCI Express extended capability structure
- Data link feature extended capability structure
- Physical layer 16.0 GT/s and 32.0 GT/s extended capabilities structures
- Lane margining at the receiver extended capability structure
- Advanced error reporting extended capability structure
The application can only access PCIe controller registers through the Hard IP Reconfiguration interface.
|Power Management Capability||Need to write back since it is required to trigger a PCI-PM entry.|
|PCI Express Capability||All the PCIe capabilities, control and status registers are for configuring the device. Write-back is required.|
|Secondary PCI Express Capability||Secondary PCIe Capability is required for configuring the device.|
|Data Link Feature Extended Capability||Data Link Capability is device specific.|
|Physical Layer 16.0 GT/s Extended Capability||Physical Layer 16G Capability is device specific.|
|Lane Margining at the Receiver Extended Capability||Margining Extended Capability is device specific.|
|Advanced Error Reporting Capability||Write-back to error status registers is required for TLP Bypass.|
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