4.4.2. Command and Status Signals
|Signal Name||Direction||Descriptions/Notes||Clock Domain|
|lnX_pipe_direct_rxstandby_i||Input||Synchronous rxstandby signal||pipe_direct_pld_tx_clk_out_o|
|lnX_pipe_direct_powerdown_i[1:0]||Input||PHY power state control signals||pipe_direct_pld_tx_clk_out_o|
Gen1-5 rate change control signals:
|lnX_pipe_direct_txdetectrx_i||Input||Receiver detect control signal||pipe_direct_pld_tx_clk_out_o|
|lnX_pipe_direct_rxtermination_i||Input||Controls the presence of receiver terminations. This is a PIPE signal mainly intended for USB usage. Intel recommends driving this signal high (default).
|lnX_pipe_direct_pclkchangeack_i||Input||Asserted by the MAC when a PCLK rate change or, if required, width change is complete and stable.||pipe_direct_pld_tx_clk_out_o|
|lnX_pipe_direct_tx_transfer_en_o||Output||This signal indicates when the EMIB is ready in PIPE mode. The soft IP controller must release the per-lane lnX_pipe_direct_pld_pcs_rst_n_i signal out of reset after the per-lane lnX_pipe_direct_tx_transfer_en_o signal is asserted.||pipe_direct_pld_tx_clk_out_o|
Indicates whether the PHY is active or in standby mode.
This signal is asserted by the PHY when it is ready for the MAC to change the clock rate.
Reflects the state of the high-speed receiver. A 1 on this bit indicates Rx is detected.
Note: The only status applicable to the PIPE SerDes architecture mode is "Receiver detected".
|lnX_pipe_direct_phystatus_o||Output||Indicates the completion of several PHY functions including stable PCLK, after reset deassertion, power management state transitions, rate change and receiver detection.||pipe_direct_pld_tx_clk_out_o|
This is the Receiver CDR lock indicator.
If this signal is deasserted when it is expected to be asserted, it indicates a fault condition and the receiver should be reset.
This is the Receiver CDR data lock indicator.
Note: This signal will go low when the Soft IP Controller instructs the R-Tile Avalon Streaming IP to start an evaluation of the far end transmitter TX EQ settings (by setting the RxEqEval bit in the Rx Control 3 register). Once the evaluation is completed, the R-Tile Avalon Streaming IP will provide a Figure of Merit value and drive this signal high. For additional details on the Equalization sequence, refer to section 9.10 of the PIPE Specification 5.1.1.