Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

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ID 683499
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Design Planning for Partial Reconfiguration A. Intel® Quartus® Prime Standard Edition User Guides
1. Design Planning for Partial Reconfiguration x
1.1. Terminology 1.2. An Example of a Partial Reconfiguration Design 1.3. Partial Reconfiguration Modes 1.4. Partial Reconfiguration Design Flow 1.5. Freeze Logic for PR Regions 1.6. Implementation Details for Partial Reconfiguration 1.7. Example of a Partial Reconfiguration Design with an External Host 1.8. Example Partial Reconfiguration with an Internal Host 1.9. Partial Reconfiguration Project Management 1.10. Programming Files for a Partial Reconfiguration Project 1.11. On-Chip Debug for PR Designs 1.12. Partial Reconfiguration Known Limitations 1.13. Document Revision History
1.1. Terminology x
1.1.1. Determining Resources for Partial Reconfiguration
1.3. Partial Reconfiguration Modes x
1.3.1. SCRUB Mode 1.3.2. AND/OR Mode 1.3.3. Programming File Sizes for a Partial Reconfiguration Project
1.4. Partial Reconfiguration Design Flow x
1.4.1. Design Partitions for Partial Reconfiguration 1.4.2. Incremental Compilation Partitions for Partial Reconfiguration 1.4.3. Partial Reconfiguration Controller Instantiation in the Design 1.4.4. Wrapper Logic for PR Regions
1.4.3. Partial Reconfiguration Controller Instantiation in the Design x
1.4.3.1. Component Declaration of the PR Control Block and CRC Block in VHDL 1.4.3.2. Instantiating the PR Control Block and CRC Block in VHDL 1.4.3.3. Instantiating the PR Control Block and CRC Block in Verilog HDL
1.5. Freeze Logic for PR Regions x
1.5.1. Clocks and Other Global Signals for a PR Design 1.5.2. Floorplan Assignments for PR Designs
1.6. Implementation Details for Partial Reconfiguration x
1.6.1. Interface with the PR Control Block through a PR Host 1.6.2. Partial Reconfiguration Pins 1.6.3. PR Control Signals Interface 1.6.4. Reconfiguring a PR Region 1.6.5. Partial Reconfiguration Cycle Waveform
1.7. Example of a Partial Reconfiguration Design with an External Host x
1.7.1. Example of Using an External Host with Multiple Devices
1.9. Partial Reconfiguration Project Management x
1.9.1. Create Reconfigurable Revisions 1.9.2. Compiling Reconfigurable Revisions 1.9.3. Timing Closure for a Partial Reconfiguration Project 1.9.4. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs)
1.10. Programming Files for a Partial Reconfiguration Project x
1.10.1. Generating Required Programming Files 1.10.2. Generate PR Programming Files with the Convert Programming Files Dialog Box
1.10.2. Generate PR Programming Files with the Convert Programming Files Dialog Box x
1.10.2.1. Generating a .pmsf File from a .msf and .sof Input File 1.10.2.2. Generating a .rbf File from a .pmsf Input File 1.10.2.3. Create a Merged .msf File from Multiple .msf Files 1.10.2.4. Generating a Merged .pmsf File from Multiple .pmsf Files 1.10.2.5. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode 1.10.2.6. Enable Bitstream Decryption Option
1.12. Partial Reconfiguration Known Limitations x
1.12.1. Memory Blocks Initialization Requirement for PR Designs 1.12.2. M20K RAM Blocks in PR Designs 1.12.3. MLAB Blocks in PR designs 1.12.4. Implementing Memories with Initialized Content 1.12.5. Initializing M20K Blocks with a Double PR Cycle
1.12.2. M20K RAM Blocks in PR Designs x
1.12.2.1. Limitations When Using Stratix V Production Devices
1. Design Planning for Partial Reconfiguration
A. Intel® Quartus® Prime Standard Edition User Guides

1.3.2. AND/OR Mode

The AND/OR mode refers to how the bits are rewritten. Partial reconfiguration with AND/OR uses a two-pass method.

Simplistically, this can be compared to bits being ANDed with a MASK, and ORed with new values, allowing multiple PR regions to vertically overlap a single column. In the first pass, all the bits in the CRAM frame for a column passing through a PR region are ANDed with '0's while those outside the PR region are ANDed with '1's. After the first pass, all the CRAM bits corresponding to the PR region are reset without modifying the static region. In the second pass for each CRAM frame, new data is ORed with the current value of 0 inside the PR region, and in the static region, the bits are ORed with '0's so they remain unchanged. The programming file size of a PR region using the AND/OR mode could be twice the programming file size of the same PR region using SCRUB mode.

Figure 5. AND/OR ModeThis is the floorplan of a FPGA using AND/OR mode, with two PR regions, with columns that overlap.
Note: If you have overlapping PR regions in your design, you must use AND/OR mode to program all PR regions, including PR regions with no overlap. The Intel® Quartus® Prime software will not permit the use of SCRUB mode when there are overlapping regions. If none of your regions overlap, you can use AND/OR, SCRUB, or a mixture of both.
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