4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description
Use the IP Catalog (Tools > IP Catalog) and parameter editor to easily configure the IP. The Shift Register (RAM-based) Intel® FPGA IP is implemented in the embedded memory block with simple dual-port RAM. You can select the RAM block type according to the capacity you require. The capacity that is represented by the width and the depth of the memory block depends on the TAP_DISTANCE, NUMBER_OF_TAPS, and WIDTH parameters of the Shift Register (RAM-based) Intel® FPGA IP.
For the features and capacities of the typical memory block, refer to the chapter of your device handbook that contains information about TriMatrix embedded memory blocks.
The Shift Register (RAM-based) Intel® FPGA IP supports single-bit and multiple-bit data shifting at one clock cycle, depending on the width of the shiftin and shiftout ports. For example, if the shiftin and shiftout ports are single-bit data, only one bit is shifted per clock cycle. If the shiftin and shiftout ports are multiple-bit data, such as one-word data (8-bit), the whole word is shifted per clock cycle.
The IP also supports output taps at certain points in the shift register chain, but the tap points must be evenly spaced. You set the space between taps in the parameter editor.
Figure (a) in Tapping Data at Certain Points of the Shift Register Chain shows a traditional 12-word-depth shift register. Figure (b) shows how the data in the shift register chain are being tapped at even spaces (1st, 4th, 7th, and 10th) at the output taps of the Shift Register (RAM-based) Intel® FPGA IP.
- The Shift Register (RAM-based) Intel® FPGA IP depicted here has TAP_DISTANCE = 3 and NUMBER_OF_TAPS = 4.
- The tapped data is output to taps[31..0]. Note that taps[31..0] is a 32-bit output because it taps four words at one time. The first word from the MSB of the taps (taps[31..24]) represents the first data and is followed by the 4th data, 7th data, and 10th data.
- The shiftout[7..0] word is equivalent to taps[31..24].
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