Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 9/26/2022

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Document Table of Contents SCFIFO Signals

Table 61.  SCFIFO Input and Output Ports Description
Signal Direction Required Description
clk Input Yes FIFO Write Clock and Read Clock.
aclr Input No Active-high reset signal that feeds the asynchronous clear pins of clk domain flip-flops.

This reset is not synchronized within the IP, and hence, user logic should ensure it is de-asserted synchronously to clk whenever appropriate.

This signal only takes effect if USE_ACLR_PORT is enabled.

  • 0 = reset inactive
  • 1 = reset active
sclr Input No Active-high reset signal that feeds the synchronous clear pins of clk domain flip-flops. Reset sequence requirements must be followed.
  • 0 = request inactive
  • 1 = request active
w_req Input Yes FIFO write request. This signal is expected to be inactive during reset.
  • 0 = request inactive
  • 1 = request active
w_data[FIFO_WIDTH-1:0] Input Yes FIFO Write Data. This bus presents the data to be stored into the FIFO when there is a write request. The value is taken by the FIFO only when w_req is active, and the FIFO is not full (i.e. w_full = 1).
w_full Output No FIFO Write Full. This signal indicates whether the space remained in the FIFO is about to run-out. When this signal asserts, further w_req is ignored.
Note: Due to internal pipeline stages to improve Fmax, the actual usable space is a few entries less than that being configured to prevent data loss.
  • 0 = FIFO is not full
  • 1 = FIFO is (near) full
r_req Input Yes FIFO Read Request / Read Ready. In order to achieve the highest possible Fmax, the use model of this signal is slightly different from the normal zero read to data ready latency FIFO.

User application is expected to assert this signal at the appropriate time to indicate its readiness to take in data some clock cycles (L) from now. At L clock later, r_valid shall be asserted if there is data available, or de-asserted if there is no data available at r_data port.

This is analogous to the Avalon® streaming non-zero read latency valid/ready interface semantics and implies enough buffer spaces are allocated in downstream user application to consume in-flight data.

  • L = 5 when RAM_BLK_TYPE is “MLAB”
  • L = 6 when RAM_BLK_TYPE is “M20K”
  • 0 = read request inactive
  • 1 = read request active
r_data[FIFO_WIDTH-1:0] Output Yes FIFO Read Data. This bus presents the data corresponds to each read request which have taken place some clock cycles earlier on. The read data is only valid in the clock cycle when r_valid asserts.
r_empty Output No FIFO Read Empty. Indicate whether there is still data word remained in the FIFO. This effectively is a pipelined version of r_usedw == 0.

This signal may be used by user application for monitoring purpose, or to initiate a series of read requests.

  • 0 = RAM block is not empty
  • 1 = RAM block is empty
r_valid Output No FIFO Read Data Valid. Indicate whether the data at r_data output port is valid. Each r_valid assertion correspond to a previous read request/ready. Due to read request to data ready latency introduced by internal pipeline stages, this signal can still be asserted for several clocks after r_empty asserts. When r_valid asserts, data must be taken by the user application; else, it will be lost.

The r_valid and r_req interface is analogous to the Avalon® streaming valid and ready semantics with non-zero read latency.

  • 0 = data is not valid
  • 1 = data is valid
w_ready Output Yes Active-low write-protect signal to gate data on the write port, before the delayed w_full asserts.