Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 9/26/2022
Document Table of Contents

3.9. Resource and Timing Optimization Feature in MLAB Blocks

The Intel® Stratix® 10 embedded memory block allow users to access two different read addresses from a physical MLAB cell. With this feature, only one MLAB block is used to read two separate addresses, improving the timing performance and optimizing user design in terms of logic elements. This feature is available by default in all Intel® Stratix® 10 devices; when MLAB is directly instantiated via atom.

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