Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 9/26/2022

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4.4.4. Performance Considerations

A wider FIFO is implemented using either multiple narrow instances or a single wide instance of these building blocks. You can choose based on empirical data or through parameters.

In the FIFO2 Intel® FPGA IP core, the Fmax has higher priority than latency. To achieve the targeted Fmax, the design will be piped when necessary. Use the following estimated pipe stages (or latency) as guidelines:
Operation Estimated Pipe Stages (Latency)
write to data available in storage ~2 read clocks
write pointer binary-to-gray conversion ~2 read clocks
write pointer cross-over to read logic ~4 read clocks
write pointer gray-to-binary conversion ~2 read clocks
write pointer and read pointer comparison result ~2 read clocks
user read to data available ~6 read clocks