Intel® Stratix® 10 Embedded Memory User Guide

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ID 683423
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Embedded Memory Overview 2. Intel® Stratix® 10 Embedded Memory Architecture and Features 3. Intel® Stratix® 10 Embedded Memory Design Considerations 4. Intel® Stratix® 10 Embedded Memory IP References 5. Intel Stratix 10 Embedded Memory Design Example 6. Intel® Stratix® 10 Embedded Memory User Guide Archives 7. Document Revision History for the Intel® Stratix® 10 Embedded Memory User Guide
1. Intel® Stratix® 10 Embedded Memory Overview x
1.1. Intel® Stratix® 10 Embedded Memory Features
2. Intel® Stratix® 10 Embedded Memory Architecture and Features x
2.1. Byte Enable in Intel® Stratix® 10 Embedded Memory Blocks 2.2. Address Clock Enable Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code Support 2.5. Force-to-Zero 2.6. Coherent Read Memory 2.7. Freeze Logic 2.8. True Dual Port Dual Clock Emulator 2.9. 'X' Propagation Support in Simulation 2.10. Intel® Stratix® 10 Supported Embedded Memory IPs 2.11. Intel® Stratix® 10 Embedded Memory Clocking Modes 2.12. Intel® Stratix® 10 Embedded Memory Configurations 2.13. Initial Value of Read and Write Address Registers
2.1. Byte Enable in Intel® Stratix® 10 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code Support x
2.4.1. Parity Bit 2.4.2. ECC Parity Flip 2.4.3. ECC Read-During-Write Behavior 2.4.4. Error Correction Code Truth Table
2.6. Coherent Read Memory x
2.6.1. Forwarding Logic
2.11. Intel® Stratix® 10 Embedded Memory Clocking Modes x
2.11.1. Single Clock Mode 2.11.2. Read/Write Clock Mode 2.11.3. Input/Output Clock Mode 2.11.4. Asynchronous/Synchronous Clears in Clocking Modes 2.11.5. Output Read Data in Simultaneous Read/Write 2.11.6. Independent Clock Enables in Clocking Modes
2.12. Intel® Stratix® 10 Embedded Memory Configurations x
2.12.1. Mixed-Width Port Configurations
3. Intel® Stratix® 10 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Customize Read-During-Write Behavior 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Including the Reset Release Intel® FPGA IP in Your Design 3.9. Resource and Timing Optimization Feature in MLAB Blocks 3.10. Consider the Memory Depth Setting
3.3. Customize Read-During-Write Behavior x
3.3.1. Same-Port Read-During-Write Mode 3.3.2. Mixed-Port Read-During-Write Mode
4. Intel® Stratix® 10 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs 4.2. eSRAM Intel® FPGA IP 4.3. FIFO Intel® FPGA IP 4.4. FIFO2 Intel® FPGA IP 4.5. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. RAM and ROM Interface Signals 4.1.8. Changing Parameter Settings Manually
4.1.8. Changing Parameter Settings Manually x
4.1.8.1. RAM and ROM Parameter Settings
4.2. eSRAM Intel® FPGA IP x
4.2.1. Release Information for eSRAM Intel® FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Intel® FPGA IP Parameters 4.2.4. eSRAM Intel® FPGA IP Interface Signals 4.2.5. eSRAM Intel® FPGA IP Simulation Walk-Through 4.2.6. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications 4.2.2.2. eSRAM Usage Model
4.3. FIFO Intel® FPGA IP x
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. FIFO Signals 4.3.3.5. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. FIFO2 Intel® FPGA IP x
4.4.1. Release Information for FIFO2 Intel® FPGA IP 4.4.2. Configuration Methods 4.4.3. Fmax Target Measuring Methodology 4.4.4. Performance Considerations 4.4.5. FIFO2 Intel® FPGA IP Features 4.4.6. FIFO2 Intel® FPGA IP Parameters 4.4.7. FIFO2 Intel® FPGA IP Interface Signals 4.4.8. Reset and Clock Schemes
4.4.5. FIFO2 Intel® FPGA IP Features x
4.4.5.1. FIFO2 Specifications
4.4.6. FIFO2 Intel® FPGA IP Parameters x
4.4.6.1. FIFO2 Parameter Settings
4.4.7. FIFO2 Intel® FPGA IP Interface Signals x
4.4.7.1. SCFIFO Signals 4.4.7.2. DCFIFO Signals
4.4.8. Reset and Clock Schemes x
4.4.8.1. Clock Domains 4.4.8.2. Reset
4.4.8.2. Reset x
4.4.8.2.1. FIFO2 Intel® FPGA IP Reset Guidelines
4.5. Shift Register (RAM-based) Intel® FPGA IP x
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.5.5. Shift Register Ports and Parameters Setting
5. Intel Stratix 10 Embedded Memory Design Example x
5.1. FIFO and FIFO2 Design Example
5.1. FIFO and FIFO2 Design Example x
5.1.1. Generating the Design Example 5.1.2. Simulating the Design Example
5.1.2. Simulating the Design Example x
5.1.2.1. Simulation Results
1. Intel® Stratix® 10 Embedded Memory Overview
2. Intel® Stratix® 10 Embedded Memory Architecture and Features
3. Intel® Stratix® 10 Embedded Memory Design Considerations
4. Intel® Stratix® 10 Embedded Memory IP References
5. Intel Stratix 10 Embedded Memory Design Example
6. Intel® Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Intel® Stratix® 10 Embedded Memory User Guide

4.1.7. RAM and ROM Interface Signals

Table 28.  Interface Signals of the Intel® Stratix® 10 RAM and ROM IPs
Signal Direction Required Description
data_a Input Optional Data input to port A of the memory.

The data_a port is required for all RAM operation modes:

  • SINGLE_PORT
  • DUAL_PORT
  • BIDIR_DUAL_PORT
  • QUAD_PORT
address_a Input Yes Address input to port A of the memory.

The address_a signal is required for all operation modes.

address2_a Input Yes

(for simple quad-port)

Read address input to port A of the memory.

The address2_a signal is required if the operation_mode parameter is set to QUAD_PORT.

wren_a Input Optional Write enable input for address_a port.

The wren_a signal is required all RAM operation modes:

  • SINGLE_PORT
  • DUAL_PORT
  • BIDIR_DUAL_PORT
  • QUAD_PORT
rden_a Input Optional Read enable input for address_a port. The rden_a signal is supported depending on your selected memory mode and memory block.
byteena_a Input Optional Byte enable input to mask the data_a port so that only specific bytes, nibbles, or bits of the data are written.

The byteena_a port is not supported in the following conditions:

  • If implement_in_les parameter is set to ON
  • If operation_mode parameter is set to ROM
addressstall_a Input Optional Address clock enable input to hold the previous address of address_a port for provided that the addressstall_a port is high.
q_a Output Yes Data output from port A of the memory.

The q_a port is required if the operation_mode parameter is set to any of the following values:

  • SINGLE_PORT
  • BIDIR_DUAL_PORT
  • QUAD_PORT
  • ROM
The width of q_a port must be equal to the width of data_a port.
data_b Input Optional Data input to port B of the memory.

The data_b port is required if the operation_mode parameter is set to BIDIR_DUAL_PORT and QUAD_PORT .

address_b Input Optional Address input to port B of the memory.

The address_b port is required if the operation_mode parameter is set to the following values:

  • DUAL_PORT
  • BIDIR_DUAL_PORT
  • QUAD_PORT
address2_b Input Yes

(for simple quad-port)

Read address input to port B of the memory.

The address2_b is required if the operation_mode parameter is set to QUAD_PORT.

wren_b Input Yes Write enable input for address_b port.

The wren_b port is required if operation_mode is set to BIDIR_DUAL_PORT and QUAD_PORT .

rden_b Input Optional Read enable input for address_b port. The rden_b port is supported depending on your selected memory mode and memory block
byteena_b Input Optional Byte enable input to mask the data_b port so that only specific bytes, nibbles, or bits of the data are written.

The byteena_b port is not supported in the following conditions:

  • If implement_in_les parameter is set to ON
  • If operation_mode parameter is set to SINGLE_PORT, DUAL_PORT, or ROM
q_b Output Yes Data output from port B of the memory. The q_b port is required if the operation_mode is set to the following values:
  • DUAL_PORT
  • BIDIR_DUAL_PORT
  • QUAD_PORT

The width of q_b port must be equal to the width of data_b port.

clock0 Input Yes The following describes which of your memory clock must be connected to the clock0 port, and port synchronization in different clocking modes:
  • Single clock: Connect your single source clock to clock0 port. All registered ports are synchronized by the same source clock.
  • Read/Write: Connect your read clock to clock0 port. All registered ports related to write operation, such as data_a port, address_a port, wren_a port, and byteena_a port are synchronized by the write clock.
  • Input Output: Connect your input clock to clock0 port. All registered input ports are synchronized by the input clock.
  • Independent clock: Connect your port A clock to clock0 port. All registered input and output ports of port A are synchronized by the port A clock.
clock1 Input Optional The following describes which of your memory clock must be connected to the clock1 port, and port synchronization in different clocking modes:
  • Single clock: Not applicable. All registered ports are synchronized by clock0 port.
  • Read/Write: Connect your read clock to clock1 port. All registered ports related to read operation, such as address_b port and rden_b port are synchronized by the read clock.
  • Input Output: Connect your output clock to clock1 port. All the registered output ports are synchronized by the output clock.
  • Independent clock: Connect your port B clock to clock1 port. All registered input and output ports of port B are synchronized by the port B clock.
clocken0 Input Optional Clock enable input for clock0 port.
clocken1 Input Optional Clock enable input for clock1 port.
eccstatus Output Optional A bit wide error correction status port. Indicate whether the data that is read from the memory has an error in single-bit with correction, fatal error with no correction, or no error bit occurs.

The eccstatus port is supported if all the following conditions are met:

  • operation_mode parameter is set to DUAL_PORT
  • ram_block_type parameter is set to M20K
  • width_a and width_b parameter have the same value
  • Byte enable is not used
eccencbypass Input Optional When active, this port allow user to inject parity flip bits through eccencparity ports. When inactive, parity flip bits will be generated using internal ecc encoder. This port can only be used when enable_ecc_encoder_bypass is set to “TRUE”.
eccencparity Input Optional When eccencbypass is active, user can inject 8-bit parity flip through eccencparity port. This port can be used only when enable_ecc_encoder_bypass is set to “TRUE”.
data Input Yes Data input to the memory. The data port is required and the width must be equal to the width of the q port.
wraddress Input Yes Write address input to the memory.
wren Input Yes Write enable input for wraddress port. The wren port is required.
rdaddress Input Yes Read address input to the memory.
rden Input Optional Read enable input for rdaddress port.
byteena Input Optional Byte enable input to mask the data port so that only specific bytes, nibbles, or bits of data are written. It is supported in Intel® Stratix® 10 devices when you set the ram_block_type parameter to MLAB.
wraddressstall Input Optional Write address clock enable input to hold the previous write address of wraddress port for as long as the wraddressstall port is high.
rdaddressstall Input Optional Read address clock enable input to hold the previous read address of rdaddress port for as long as the rdaddressstall port is high.
q Output Yes Data output from the memory.
inclock Input Yes The following describes which of your memory clock must be connected to the inclock port, and port synchronization in different clocking modes:
  • Single clock: Connect your single source clock to inclock port and outclock port. All registered ports are synchronized by the same source clock.
  • Read/Write: Connect your write clock to inclock port. All registered ports related to write operation, such as data port, wraddress port, wren port, and byteena port are synchronized by the write clock.
  • Input/Output: Connect your input clock to inclock port. All registered input ports are synchronized by the input clock.
outclock Input Yes The following describes which of your memory clock must be connected to the outclock port, and port synchronization in different clocking modes:
  • Single clock: Connect your single source clock to inclock port and outclock port. All registered ports are synchronized by the same source clock.
  • Read/Write: Connect your read clock to outclock port. All registered ports related to read operation, such as rdaddress port and rdren port are synchronized by the read clock.
  • Input/Output: Connect your output clock to outclock port. The registered q port is synchronized by the output clock.
inclocken Input Optional Clock enable input for inclock port.
outclocken Input Optional Clock enable input for outclock port.
aclr Input Optional Asynchronously clear the output ports. The asynchronous clear effect on the registered ports can be controlled through their corresponding clear parameter, such as outdata_aclr_a and outdata_aclr_b.
sclr Input Optional Synchronously clear the output ports. The synchronous clear effect on the registered ports can be controlled through their corresponding parameter, such as outdata_sclr_a and outdata_sclr_b.
Note: When running the embedded memory simulation model, you must ensure that you do not provide “X” or dont_care as inputs to the simulation model. Providing “X” or don’t_care may result in unexpected behavior in simulation.
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