Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 9/26/2022
Document Table of Contents

4.3.17. Reset Scheme

During power-up, the registers in the Intel® Stratix® 10 devices are in undefined power and reset states. To guarantee correct functionality, reset the FIFO Intel® FPGA IP core upon completion of configuration by asserting either the sclr or aclr signal.

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