Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 9/26/2022
Document Table of Contents

3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously

When you are running a simulation using the embedded memory simulation model on an event-based simulator, you must avoid changing the clock signals and other control signals (i.e., address and data signals) simultaneously. For example, if you change the read enable signal at the same time when a positive clock edge arrives, the simulator either schedules the read enable signal to happen after or before the positive clock edge. In other words, a delta delay will occur between the read enable and positive clock edge, which can result in an unexpected behavior in simulation. To avoid this unexpected behavior, Intel® recommends that you insert delays between the clock signals and other control signals.

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