2.3. Asynchronous Clear and Synchronous Clear
If your RAM does not use output registers, the RAM outputs are cleared using the latch asynchronous clear (aclr). The (aclr) signal is generated at any time. The internal logic extends the clear pulse until the next rising edge of the output clock. When the aclr signal asserts, the outputs are cleared and stay cleared until the next read cycle.
For the synchronous clear (sclr) signal, the RAM outputs are cleared at the next rising edge of the output clock when the (sclr) signal is asserted. The outputs will stay cleared until the next read cycle.