Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 9/26/2022
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2.3. Asynchronous Clear and Synchronous Clear

The Intel® Stratix® 10 M20K and MLAB embedded memory blocks support asynchronous clear and synchronous clear on output latches and output registers.

If your RAM does not use output registers, the RAM outputs are cleared using the latch asynchronous clear (aclr). The (aclr) signal is generated at any time. The internal logic extends the clear pulse until the next rising edge of the output clock. When the aclr signal asserts, the outputs are cleared and stay cleared until the next read cycle.

For the synchronous clear (sclr) signal, the RAM outputs are cleared at the next rising edge of the output clock when the (sclr) signal is asserted. The outputs will stay cleared until the next read cycle.

Note: Both aclr and sclr signals must be used separately for each RAM configuration.
Figure 5. Behavior of Asynchronous Clear and Synchronous Clear in Registered Mode
Figure 6. Behavior for Asynchronous Clear and Synchronous Clear in Unregistered Mode