Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 9/26/2022
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4.2.4. eSRAM Intel® FPGA IP Interface Signals

The following table lists the input and output signals of the eSRAM Intel® FPGA IP interface.
Table 35.  eSRAM Intel® FPGA IP Input and Output Signals
Signal Direction Width Description
refclk Input 1 Provide a PLL reference clock. This clock must be stable and free-running at device power-up for a successful configuration.
esram2f_clk Output 1 Core clock provided by the eSRAM to the fabric. Use this clock to drive core logics that are interfacing with the eSRAM. Otherwise, proper cross-clock domain circuitry is expected.
c<channel_number>_data_0 Input 1-72
  • 72 for clear channel data, or
  • 64 when ECC is enabled, or
  • 72 when ECC Bypass is enabled, the MSB (most significant bit) of data (data[71:64]) represents the parity bits.
c<channel_number>_wraddress_0 Input Range from

17–11

Write address of the memory. Dependent on how many banks are enabled in the channel.
Note: Writing to an invalid address does nothing, because the targeted bank is not powered.
c<channel_number>_wren_n_0 Input 1 Active low write enable input for the wraddress port.
c<channel_number>_rdaddress_0 Input Range from

17–11

Read address of the memory. Dependent on how many banks are enabled in the channel.
Note: If you attempt to read from an invalid address, the data returned is random and of no value.
c<channel_number>_rden_n_0 Input 1 Active low read enable input for the rdaddress port.
c<channel_number>_q_0 Output 72 or 64
  • 72 for clear channel data, or
  • 64 when ECC is enabled, or
  • 72 when ECC Bypass is enabled, the MSB of output (q[71:64]) represents the parity bits.
ECC Enabled
c<channel_number>_error_detect_0 Output 1 Asserts when an ECC error occurred on the read data retrieved from the eSRAM.
c<channel_number>_error_correct_0 Output 1 Asserts when an ECC error is successfully corrected. The memory content is not updated with the corrected data.
Dynamic ECC Bypass Enabled
c<channel_number>_eccencbypass_0 Input 1 Dynamically bypass the ECC Encoder. When active, this port allows user to inject parity bits through 8-bits MSB from data port (c<channel_number>_data_0[71:64]). When inactive, parity bits will be generated using internal ECC Encoder. This port can only be used when c<channel_number>_ecc_byp_enable parameter is set to "TRUE".
c<channel_number>_eccdecbypass_0 Input 1 Dynamically bypass the ECC Decoder. 8-bits MSB from output port (c<channel_number>_q_0[73:64]) represents the parity bits. Parity bits are not checked and the c<channel_number>_error_detect_0 and c<channel_number>_error_correct_0 signals should not assert. This port can only be used when c<channel_number>_ecc_byp_enable parameter is set to "TRUE".
Additional Options
c<channel_number>_sd_n_0 Input 1 Active low signal that dynamically shuts down channels. This signal shuts down power to periphery (active low) and memory core of the banks within the channel, with no memory data retention.

In addition to the channels that are statically shut down when choosing the number of channels to use in an eSRAM system, you can also dynamically shut down channels at run time.

Note: Memory contents are not retained when a channel is shut down.
iopll_lock2core Output 1 eSRAM IOPLL lock status.
  • High—Locked
  • Low—Unlocked or lock loss.