To maximize Fmax, there are non-resettable flops (or registers) with undefined initial power and reset states. Unless the reset state of a given interface signal is specified, you must not assume the reset the non-resettable flops to be of a specific value during power up or reset. As part of reset sequence, you must ensure that the FIFO internal stale states are flushed before normal operations are started or resumed.
The FIFO2 Intel® FPGA IP core exposes both asynchronous and synchronous clear ports per clock domain so that the user application has full control on how reset sequences, such as entering and exiting reset, should work. The clear events for both w_clk and r_clk clock domains come from the same source so that the logic in both domains are brought into or out of reset together nominally. For example, you can choose to reset the logic in one clock domain such as r_clk, instead of w_clk. However, some signals such as the FIFO fill level status take time to settle down to the right states. In this case, the user application must ensure those signals do not cause any unintentional side effect.